On January 18, 2026, TechXplore reported on a Nature Communications paper from a team at Zhejiang Lab and Fudan University: a training method called EaPU (error-aware probabilistic update) that makes memristor-based neural networks train with nearly six orders of magnitude — close to a million times — less energy than GPUs, while cutting write operations by more than 99% and extending device lifetime roughly a thousand-fold.
For an industry being squeezed by the power bill of compute, this is a rare route that attacks the problem at the hardware floor. Nothing about the model or the training objective changes; what changes is how the single most frequent hardware operation — the weight update — is executed.
EaPU: Writing Hardware Noise into the Algorithm
The root cause is a fundamental mismatch. Backpropagation assumes weight updates are deterministic and can be applied in small, precise increments. Memristors behave stochastically: the same voltage pulse produces a different conductance change every time, and device relaxation makes write errors accumulate over time. Hardware noise pollutes the gradients directly, and training collapses.
EaPU coexists with the noise instead of fighting it. When a desired weight change falls below a threshold, the algorithm skips the small write and instead applies one full-threshold pulse with probability proportional to the intended change — or skips the write entirely. In expectation, the average update stays the same, preserving training performance; in practice, writes become rare. Fewer than 0.1% of parameters need updating per step — on a 152-layer ResNet, that works out to 0.86 writes per thousand parameters.
Where the Million-Fold Energy Gap Comes From
The numbers stack in three tiers. Compared with previous memristor training approaches, EaPU trains with about 50 times less energy; compared with the state-of-the-art MADEM method, about 13 times less; compared with GPU training, the gap approaches six orders of magnitude. The team notes that numerous studies have already confirmed the energy efficiency of memristor-based in-memory computing — but write errors accumulating over time under device relaxation kept that efficiency out of reach.
The write reduction pays a second dividend: endurance. A memristor’s usable life is defined by write cycles, so cutting updates by more than two orders of magnitude extends device lifetime by roughly 1,000x. The deployment math is direct — the same hardware trains more rounds and lasts longer. There is a third-order effect worth noting for anyone sizing clusters: less writing also means less energy spent on the write path itself and less heat to dissipate, which compounds at rack scale in a way that per-chip benchmarks understate.
Validation: From Image Denoising to 152-Layer ResNets
Validation ran on two tracks. In simulation, the team tested ResNets up to 152 layers and Vision Transformers; on noisy hardware, EaPU delivered accuracy gains exceeding 60% over standard backpropagation. On physical hardware, the team built a custom 180-nanometer memristor array and ran image denoising and super-resolution tasks, achieving structural similarity indices of 0.896 and 0.933 respectively — matching or beating conventional training. Training on real analog arrays is where most memristor papers quietly give up and retreat to simulation, so having silicon-level numbers at all separates this work from the bulk of the literature.
That is the point that matters: the probabilistic scheme did not trade accuracy for energy. EaPU reshapes the magnitude distribution of updates through a probabilistic transform while keeping “the average value of the updates unchanged to guarantee training performance” — the design decision the whole method stands on.
How Far from LLM Training
Be honest about the distance to production. The physical validation ran on a small 180nm array doing image restoration, not language modeling; the simulations covered deep CNNs and ViTs, but memristor training at LLM scale remains a stated ambition rather than a result. The team points its next steps at extending EaPU to ferroelectric transistors and magnetoresistive RAM, and at training clusters for large language models. The code is publicly available on Zenodo.
For infrastructure decision-makers, this research will not change a purchase order this quarter. But it marks a scaling path fundamentally different from “stack more GPUs”: when training’s energy bottleneck lives in data movement and writes rather than computation itself, algorithm-hardware co-design is the real lever. Put EaPU on the watchlist, and wait for it to replicate on larger models.
Sources
- New memristor training method slashes AI energy use by six orders of magnitude — TechXplore
- Error-aware probabilistic training for memristive neural networks — Nature Communications
AI-assisted summary compiled from the sources above, reviewed by a human before publishing.