On August 19, Cerebras announced the CS-4, its next-generation rack-scale inference system, along with the WSE-3T “Turbo” wafer. The headline claim: up to 30x faster inference than GPUs, with a stated goal of ten times the throughput per watt of the previous generation. The Register and The Next Platform both published detailed write-ups the same day, and the first CS-4 systems are expected online later this quarter.
The most interesting decision from the company that proved “a wafer is the chip” is what it did not do: it did not build a new chip.
Not New Silicon, Just Pushed Harder
The “T” in WSE-3T stands for Turbo, but this is not new silicon. The process node, the 46,225 square-millimeter wafer area, the transistor count, the core count, and the 44 GB of on-wafer SRAM are all identical to the two-year-old WSE-3. What changed is power delivery: Cerebras says its new design can push twice the power through the wafer, which enables higher operating frequencies and faster token generation. The Register estimates the silicon now clocks around 2.8 GHz, up from 1.4 GHz in the previous generation.
The result is a doubling across the board. Each wafer now delivers 250 petaFLOPS of AI compute (a sparse figure), 43.2 PB/s of memory bandwidth, and 2.4 Tbps of off-die connectivity — double the old 1.2 Tbps. Chip-to-chip latency has been cut from five microseconds to two, which turns out to matter as much as any bandwidth number.
Inside the Rack: Backpacks, Power Shelves, and a 2D Torus
Each CS-4 holds up to three WSE-3T wafers in a “backpack” form factor: self-contained modules with all control electronics on board that plug into the back of the rack, while the front is reserved for power shelves. Like NVIDIA’s NVL72 and AMD’s Helios, the CS-4 breaks compute, power delivery, and cabling into a modular architecture meant for datacenter deployment and maintenance. The Register estimates total system power between 120 and 140 kW. That sounds monstrous, but next to the 240 to 250 kW racks AMD and NVIDIA are expected to ship later this year, it looks almost conservative.
The interconnect is the other notable piece. CS-4 drops the switches: chips talk to each other directly over a 2D torus, a grid whose ends wrap around to the opposite side. Cerebras says the topology can scale to models of up to 50 trillion parameters, a size no shipped model currently reaches. If you prefer a switched fabric, RoCE over Ethernet is supported — at somewhat higher latency. Low latency is what lets Cerebras use the simplest form of multi-chip inference, pipeline parallelism: model weights are spread across wafers, and work flows through them one chip after another, no tensor-parallel gymnastics required.
Splitting Inference: Prefill Goes to Trainium and Instinct
The bigger architectural shift is that Cerebras is no longer trying to run the entire inference stack on its own silicon. The compute-hungry prompt-processing stage — prefill — is offloaded to AWS Trainium accelerators and AMD Instinct GPUs, while the Cerebras wafers handle the stage they are uniquely suited for: decode, where the enormous on-wafer SRAM keeps weights and KV-caches close to the compute. Instead of needing thousands of accelerators to serve a trillion-parameter model, a few dozen wafers can do, depending on the precision at which the weights are stored.
Great Numbers, With Caveats
The performance data point making the rounds comes from Artificial Analysis: on a single CS-4 system, gpt-oss-120b serves up to 4,400 tokens per second per user, against roughly 350 tokens per second on the fastest GPU-based inference service today. That is the kind of gap that changes product decisions for latency-sensitive applications.
The Register adds two sober footnotes. First, the 250 PFLOPS figure relies on sparsity; as dense FP16 it lands nearer 25 PFLOPS — still impressive, less spectacular than the slide suggests. Second, the peak memory bandwidth is likely theoretical; the WSE-3 could never saturate its own SRAM during LLM inference, and nothing about the Turbo wafer suggests that changed.
What It Means for Developers and Buyers
Three takeaways. First, the rack is now the unit of competition: NVIDIA’s NVL72, AMD’s Helios, and Cerebras’s CS-4 all define deployment by the rack, and procurement conversations shift from “how many cards” to “how many racks.” Second, heterogeneous inference is mainstream — if even Cerebras concedes that prefill does not need its wafers, there is little excuse for bolting every stage of your inference pipeline to one kind of accelerator. Third, with first systems landing this quarter, teams choosing backends for latency-critical voice or agentic workloads have a genuinely new option to benchmark, alongside the incumbents they already test.
Sources
- Introducing Cerebras CS-4 — Cerebras
- Cerebras CS-4 rack systems juice chips for every last drop of AI performance — The Register
- Cerebras Overclocks WSE-3 Waferscale Engine to Boost Inference in “Nexus” CS-4 — The Next Platform
AI-assisted summary compiled from the sources above, reviewed by a human before publishing.