On February 10, 2026, Cadence, the EDA heavyweight, announced the ChipStack AI Super Agent, positioned as “the world’s first agentic workflow for automating chip design and verification.” Reuters reported the same day that the tool targets a bottleneck in chip design flows, with tasks sped up by as much as ten times. It is available now in early access, and Altera, NVIDIA, Qualcomm, and Tenstorrent are already in early deployment.
Here is why this matters beyond the semiconductor press: agentic software has entered one of the hardest verticals in existence. Writing RTL, building testbenches, and running regression suites — deeply specialized work where mistakes cost millions — now has a commercial product that executes it autonomously.
What the 10X Claim Actually Covers
Cadence’s “10X productivity improvement” has a defined scope: coding designs and testbenches, creating test plans, orchestrating regression testing, and debugging and automatically fixing issues.
In agent terms, this workflow pushes an agent into four stages of front-end design at once: generation (code and test plans), execution (regressions), observation (debugging), and correction (auto-fixes). Unlike an assistant that autocompletes code, the Super Agent is built to independently orchestrate multiple “virtual engineers” and hand back finished design and verification work. SiliconANGLE’s coverage likewise emphasizes that the system aims to change how engineers automate chip design.
Cadence President and CEO Anirudh Devgan framed it as an extension of the company’s “design-for-AI and AI-for-design strategy”: AI agents autonomously call Cadence’s underlying EDA tools — the same tools already used to design today’s most advanced AI systems.
How It Orchestrates the EDA Toolchain
The Super Agent is not a standalone product built from scratch. It hangs off Cadence’s existing AI assets: integrated with the Verisium Verification Platform, optimized through the Cadence Cerebrus Intelligent Chip Explorer, and sharing data via the JedAI data and AI platform. The official number: those AI optimization and assistant solutions have been used in more than 1,000 tapeouts.
This detail is the key to understanding vertical agents. Why can you trust RTL that a model wrote? Because it runs on a real verification toolchain, and physics-based and formal checks gate the results. The autonomy comes from a closed loop — generate, verify, repair inside one system — not from dumping generated code into an external tool for manual inspection.
Model Layer: Cloud and On-Prem Side by Side
Cadence took a pragmatic route on models: nothing is locked in. ChipStack supports cloud-based and on-premises frontier models, including the open NVIDIA Nemotron models customizable with NVIDIA NeMo, plus cloud-hosted models such as OpenAI GPT.
For the chip industry this is not a footnote. RTL under development is some of the most sensitive intellectual property anywhere; whether the agent can run inside your own data center decides whether it enters the official flow at all. Tenstorrent’s deployment is the example: they ran the agent on their own hardware for on-prem inference.
Numbers from Early Customers
The four early customers gave concrete measurements:
- Altera (the FPGA company spun out of Intel): Arvind Vidyarthi, senior director of engineering, reported verification effort reduced roughly 10X in some areas
- Tenstorrent: a three-month evaluation across three critical design blocks cut verification time by up to 4X
- NVIDIA: Timothy Costa, GM of Industrial and Computational Engineering, cited Mental Models and automated formal test plan generation, paired with NVIDIA accelerated computing
- Qualcomm: Paul Penzes, VP of engineering, confirmed an evaluation for a broad user base with “encouraging” results
Ten is the vendor ceiling and four is Tenstorrent’s measured floor — the gap between them is the usual story with such claims: the denominator is whatever process you started from.
What It Means for Developers and Product Teams
Paul Cunningham, Cadence’s VP of R&D, stated the motivation bluntly: the industry faces a “senior deficit in engineering talent.” Chip complexity is rising, AI is pushing silicon demand higher, and the labor supply is not keeping up — automation is becoming mandatory, not optional.
Two takeaways for anyone building agentic products. First, the moat for vertical agents sits in toolchain integration, not raw model capability; Cadence’s 1,000-tapeout track record and verification platform are what customers actually buy. Second, on-prem inference demand will grow as agents enter high-sensitivity industries — model flexibility is shifting from nice-to-have to procurement prerequisite.
Sources
- Cadence Unleashes ChipStack AI Super Agent, Pioneering a New Frontier in Chip Design and Verification — Cadence
- Cadence introduces an AI agent to speed up computer chip design — Reuters
- Cadence announces ChipStack ‘Super Agent’ system for chip design verification — SiliconANGLE
AI-assisted summary compiled from the sources above, reviewed by a human before publishing.